FIG. 19 is a schematic view showing the atomic arrangement of Si and C in the perfect 4H—SiC crystal. The crystal lattices of semiconductors are not perfect even in the case where they do not contain any impurities, some amount of vacancies and interstitials is always present to maintain the thermodynamic equilibrium. As shown in FIG. 20, the point defects in a compound semiconductor can be classified as follows:
a) a vacancy: in the case where an atom is removed from its site.
b) an interstitial: in the case where an atom occupies a site different from a regular. In the case where an interstitial is of the same species as the host lattice, it is called self-interstitial. Otherwise, it is called interstitial impurity.
c) a Frenkel pair: in the case where a vacancy is located close to a self-interstitial.
d) an antisite: in the case where an atom of one sublattice is placed in the other sublattice.
e) an impurity: a foreign atom.
In addition, associations of the above defects are often possible, i.e. di-vacancy or vacancy-impurity complexes.
In the case where the periodicity of the monocrystal is perturbed by impurity atoms or crystal defects, discrete energy levels are introduced in the band gap. These levels are divided into shallow and deep levels.
The shallow level centers are usually donor or acceptor impurities. On the other hand, in contrast to shallow levels, deep level defects interact with both the conduction band and valence band and can be very efficient as centers of carrier trapping and recombination. In such a case, these defects are called electrically active and often referred as “traps”. They can influence carrier lifetime significantly even at very low concentrations.
Although SiC layers of excellent quality are available at present, they still contain native intrinsic defects which act as carrier traps and degrade materials characteristics. In particular, an intrinsic defect concentration is increased as a growth rate and a growth temperature are increased. The high thermal stability of SiC makes it usually difficult or impossible to remove these defects by a thermal treatment (anneal out). Since the increased growth rate is necessary for growing thick layers which are cost-effective, it is important to find a way to achieve low defect density in these layers.
It has been shown that defect concentration can be reduced, and the quality of a material in the state that crystal growth is completed (hereafter referred to as as-grown material) can be improved to a certain level by a high temperature thermal treatment (annealing). However, in the case of an SiC monocrystal, the improvement is not sufficient due to the above described high thermal stability. In addition, a part of intrinsic defects created by irradiation of electrons, protons, or ions can be removed by annealing, but another part is just reduced, and the lowest defect concentration is usually determined by the original as-grown material.
The electrically active defects in an as-grown SiC layer have been investigated by Zhang and others (Non Patent Document 1). In this document, the major electron traps and hole traps in an as-grown SiC layer were determined by using the Deep Level Transient Spectroscopy (DLTS) and the Minority Carrier Transient Spectroscopy (MCTS). More specifically, the traps in relation to the Ti and B impurities, and the Z1/Z2 and EH6/7 intrinsic defects in relation to electron traps were measured by these methods. In addition, the Z1/Z2 and EH6/7 traps showed the inverse correlation with the minority carrier lifetime.
Klein and others concluded that the Z1/Z2 defects have a large capture cross section for holes and dominate in limiting the minority carrier lifetime in the n-type SiC layer (Non Patent Document 2).
Kimoto and others investigated the concentration dependency of the Z1/Z2 center as the function of the ratio of carbon to silicon during the chemical vapor deposition (CVD) growth. They showed that the growth under C-rich conditions is a key factor to obtain the lower concentration of the Z1/Z2 center (Non Patent Document 3).
Storasta and others investigated the deep level in relation to the selective displacement of carbon atoms (Non Patent Document 4). The irradiation with electrons of energy below the threshold for silicon atom displacement was enough to create the Z1/Z2 and EH6/7 intrinsic defects. Consequently, they concluded that they must have relation to defects (complexes) related to either of carbon vacancies and interstitials.
Negoro and others investigated the reduction effect by annealing of the Z1/Z2 and EH6/7 traps in the as-grown material (Non Patent Document 5). By annealing at a temperature of 1700° C. or higher, a concentration of the Z1/Z2 and EH6/7 centers was decreased by one order of magnitude as compared to that in the as-grown epitaxial layer, but did not vanish completely.
It is known that, aluminum, boron, and nitrogen, etc. are ion-implanted into the surface layer, and a high temperature thermal treatment is carried out in order to make the implanted atoms electrically active in the surface layer and to utilize the surface layer as a device structure in the formation process of an SiC device. In addition, it is proposed that in the case where impurities such as boron are ion-implanted into the surface layer and the device structure is formed in the surface layer by making the impurities electrically active due to annealing, carbon is also ion-implanted simultaneously. Patent Document 1 relates to the technique for forming a p-type layer of boron that is utilized as a device structure. In the disclosed technique thereof, in order to selectively incorporate activated boron atoms into the silicon site having a shallow energy level, boron and carbon atoms are ion-implanted simultaneously into the surface layer, and electrically activated boron atoms are selectively introduced not into the carbon vacancies but into the silicon vacancies due to the existence of excess carbon interstitials in the surface layer in the case where boron atoms compete with silicon interstitials and carbon interstitials in the surface layer during annealing.
However, the object of such a technique already known is to make the impurities that have been implanted into the surface layer for forming the device structure, to be electrically active in the surface layer by annealing. Unlike the present invention described below, the above described technique does not indicate that carbon interstitials are introduced into the shallow surface layer of the as-grown SiC crystal, the carbon interstitials are diffused into a region deeper than the surface layer by the subsequent annealing, and the point defects vanish in the deep portion of the wafer.
Patent Document 1: U.S. Pat. No. 6,703,294
Non Patent Document 1: Journal of Applied Physics, Vol. 93, No. 8, pp. 4708-4714, 15 Apr. 2003
Non Patent Document 2: Applied Physics Letters, 88, 052110, 30 Jan. 2006
Non Patent Document 3: Applied Physics Letters, Vol. 79, No. 17, pp. 2761-2763, 22 Oct. 2001
Non Patent Document 4: Applied Physics Letters, Vol. 85, Issue 10, pp. 1716-1718, September 2004
Non Patent Document 5: Journal of Applied Physics, Vol. 96, No. 9, pp. 4909-4915, 1 Nov. 2004